This invention relates to a semiconductor device provided with a plurality of sense circuits using MOS transistors.
In recent years, in MOS type semiconductor memory devices, it has become common to use sense circuits to sense and read very small potential differences corresponding to the storage content of a memory cell by making use of a difference between the conductance values of a pair of MOS transistors.
The basic configuration of a conventional sense circuit is shown in FIG. 3. As shown in this figure, MOS transistors Q1 and Q2 have their sources connected in common. Also, the drain of one transistor and the gate of the other transistor are connected so that they are cross-coupled to each other. In this circuit configuration, a difference between the potentials applied to the respective gates, i.e., a difference between potentials on the nodes N1 and N2 is sensed by making use of a difference between conductance values of the MOS transistors Q1 and Q2.
An example of the pattern arrangement in the case where a plurality of sense circuits of such a configuration are formed on a semiconductor substrate is shown in FIG. 4. One sense circuit 40a comprises MOS transistors Q1 and Q2. In the pattern arrangement of FIG. 4, a plurality of such sense circuits 40a, 40b, . . . are arranged. Here, a gate electrode 41 of the MOS transistor Q1 and a gate electrode 42 of the MOS transistor Q2 are ordinarily formed by a polycrystalline silicon film. Further, a drain region 43 of the MOS transistor Q1 and a drain region 44 of the MOS transistor Q2 are formed in a self-alignment manner by injecting impurity ions thereinto by using the gate electrodes 41 and 42 as a mask.
However, the conventional semiconductor device had the following problem. Namely, a plurality of sense circuits 40a, 40b, . . . were arranged with element isolation regions (isolation regions between respective sense circuits) provided therebetween. For this reason, realization of a semiconductor device integrated to a high degree was obstructed. In order to realize a semiconductor device integrated to a high degree, drain/source regions (43, 44; 45) of MOS transistors provided in respective sense circuits must be miniaturized. However, when an attempt is made to miniaturize those source/drain regions, the impurity concentration becomes uneven, or contact resistance values of respective regions increase, so their values become uneven. In addition, in the case of forming respective regions, wiring layers, contact portions, etc., deviation of the mask positioning took place. As a result, there occurred unevenness in the transistor characteristic, resulting in lowered production yield or deteriorated performance.